1. Field of the Invention
The present invention generally relates to a method of manufacturing a multi-layer substrate, and more particularly to a method of manufacturing a flexible multi-layer substrate.
2. Description of Prior Art
Please refer to FIG. 1, which depicts a diagram of multi-layer substrate manufactured by hot pressing and adhering different layers according to prior art. Basically, a multi-layer substrate that is manufactured by hot pressing and adhering is called Sequential Lamination from double side according to prior arts. First, a core 100 with copper clad 102 is provided. A lithography process and a development process are proceeded to the copper clad 102 to form pattern thereon (as being a metal structure layer, i.e. metal lines for transmitting signals). Then, laminating a prepreg 104, another core 100 which already had the metal structure layer 102 and another prepreg 104 laminated onto, and so on. After laminating the last surface copper clad 102 on the last prepreg 104, the multi-layer substrate is hot pressed at a high temperature. Afterwards, there can be a lithography process and a development process to the last surface copper clad 102 to form a pattern thereon. Then, a solder mask 106 is coated on the last surface copper clad 102.
As aforementioned, with hot pressing and adhering called Sequential Lamination according to prior arts, the prepregs 104 between different layers with different materials are essential for making the different layers adhered to each other. Moreover, due to complication of modern circuit design, many necessary detail processes coming up with, such as drilling, plating via or hole, etching, cleaning, polishing, black oxidizing and etc. Moreover, pre-processes for the aforesaid detail processes can also be relevant and more involved. Accordingly, the prior arts are complicated with many composite materials, such as, core 100 having the copper clad 102, the prepregs 104, the solder mask 106 and etc. are needed. Therefore, one process failure can cause the whole multi-layer substrate to breakdown and decrease the yield thereof. It's not easy to control the process quality and the manufacture cost because too many materials are being used.
Besides, miniaturization for electronic productions is an unavoidable trend in this modern world. The aforesaid multi-layer substrate manufactured by hot pressing and adhering has limitation of trace pattern for size minimization. According to prior arts, the thickness of the core is about 100 μm and the thickness of the prepreg is about 50 μm, therefore, the thickness of an 8-layer substrate product is about 600 μm. In prior arts, the dielectric layers (defined as substance between two copper clads) may use numerous kinds of materials. Because the materials of the core and prepreg are composite materials, there are problems of difficult matching for the electric characteristic (such as Dk, dielectric constant) and mechanical characteristic (such as CTE, coefficient of expansion).
Furthermore, the thickness of the dielectric layer according to prior arts results in that the distance from one metal line to the adjacent one in the same metal structure layer is considerably same as the distance to the reference plane or even closer. (Theoretically, it is better for any metal line to be far way from the adjacent metal line and to be closer to the reference plane.) Then, the signal transmitted in one metal line can be easily interfered by the signal transmitted in the adjacent metal line. The electric fields and performances of the signals transmitted in the adjacent metal lines interfere with each other and cause serious problems of the signal integrity, such as, crosstalk when high-frequency signals are transmitted through a stripline, high frequency noise and backward coupling caused by parasitic inductance and parasitic capacitor of the vias.
For transmitting the high frequency signal, the present invention manufacturing the thin dielectric layers for three main purposes: (1) area of the transmission path and backflow path of the metal line is small and hardly interfered by other signals, (2) crosstalk influence can be reduced when high-frequency signal is transmitted through a stripline and the layout density of the metal lines can be increased, and (3) via can be shortened to reduce high frequency noise caused by parasitic inductance and parasitic capacitor.
When manufacturing a multi-layer substrate in PCB industry, it is better that metal lines of different substrate products can be controlled in the same impedance value, i.e. impedance matching because there are signals transmitted therebetween. The reason is: signal will split into reflection part and incidence part when the signal transmission suffers a connection interface of two metal lines of different products if the two metal lines have different impedance values. The signal integrity can be destroyed. Therefore, there will be a predetermined impedance matching when manufacturing a multi-layer substrate in the PCB industry.
Please refer to FIG. 2 and FIG. 3. FIG. 2 depicts a profile of a metal line located in a thin dielectric layer. FIG. 3 depicts a relationship diagram of an impedance value of the metal line which takes an adjacent metal layer as ground connection versus a ratio of H1/W (height from ground/width of the metal line) in the multi-layer substrate shown in FIG. 2. The metal line 201 in FIG. 2 is located in a dielectric layer. Supposing the dielectric constant of the dielectric layer is εr, the width and height of the metal line 201 are W and T. The distances to the upper and lower metal structure layer is H2 and H1 (the lower metal structure layer is taken as ground connection). FIG. 3 shows relationship between a related value of impedance √{square root over (εr)}Z0 and the ratio of H1/W for the metal line 201 shown in FIG. 2. Accordingly, for a predetermined impedance matching and a predetermined H1/H2 ratio, the solution for the ratio of H1/W is unique. Therefore, for manufacturing a smaller multi-layer substrate and still satisfy the predetermined impedance, H1 has to be smaller, i.e. the thickness of the dielectric layer has to be thinner.
Please refer to FIG. 4 and FIG. 5. FIG. 4 depicts a profile of several parallel metal lines located in a thin dielectric layer. FIG. 5 depicts a relationship diagram of a backward coupling of crosstalk versus a ratio of H1/S (height from ground/separated distance) when high-frequency signal is transmitted through the metal line in the multi-layer substrate shown in FIG. 4. The metal lines 401, 402 and 403 in FIG. 4 are located in the same dielectric layer. Supposing the dielectric constant of the dielectric layer is εr. For example, the width and height of the metal line 402 are W and T. The separated distance is S. The distances to the upper and lower metal structure layer is H2 and H1. C10, C20, C30, C12, −C12, −C13, −C23 represent parasitic capacitors between the metal lines. The signal in metal line 401 generates backward coupling to the signal in the metal line 402 at the end of the metal line 402. The formula can be described as below:V21≈b21[V0(t)−V0(t−2τD)]  (1)b21≈0.25(−C21/C22+L21/L11)  (2)
V0(t) is the signal voltage inputted at the end of the metal line 401. The τD represents distance that the signal has been transmitted. L21 and L11 represent the parasitic inductances. Formula (1) means that the value V21 representing generated crosstalk and backward coupling is proportional to the coefficient b21. FIG. 5 shows the proportional relation between the coefficient b21 and the ratio H1/S. Accordingly, with a hypothesis of predetermined S and predetermined W, the smaller the H1 gets, the smaller the coefficient b21 is, i.e. influence of the crosstalk and backward coupling is smaller. The signal integrity is better. More detail description about crosstalk, backward coupling and the high frequency noise caused by parasitic inductance and parasitic capacitor of the vias can be found in IBM J. RES. DEVELOP., VOL. 32, NO. 5, SEPTEMBER 1988.
In brief, a greatly thin dielectric layer can satisfy the request of impedance matching and is capable of further reducing the influence of crosstalk and backward coupling. Meanwhile, vias in the dielectric layers can be shortened to reduce high frequency noise caused by parasitic inductance and parasitic capacitor.
Moreover, when a high integration flexible multi-layer substrate is manufactured, effects of the mechanical characteristic (such as CTE, coefficient of expansion), warpage or twist, inner or outer stresses to the flexible multi-layer substrate and the limitation to thickness thereof have to be concerned further. Many different materials employed in the prior arts result in difficulty of the mechanical characteristic matching. The end product of the multi-layer substrate according to prior arts is thicker and losses the expected flexibility.
In conclusion, there is a need to develop a thin multi-layer substrate that takes fewer processes, fewer materials than prior arts without using prepreg. The thin dielectric layer can match with the thickness of the metal lines (metal structure layer), accordingly, to solve drawbacks of prior arts so as to promote the entire quality and yield of manufacturing the multi-layer substrate. Furthermore, the thin multi-layer substrate still keeps good signal integrity when satisfying demands of miniaturization for the multi-layer substrate, especially satisfying demands of miniaturization for the flexible multi-layer substrate.